Electromigration Effect in VLSI

Electromigration is an important issue especially in lower technology node where the cross-sectional area of metal interconnects is very less. In this article, we will discuss the phenomenon of electromigration, the effects of electromigration and the ways to prevent the electromigration issue.    Electromigration: When a high current density passes through a metal interconnect, the … Read more

Inputs for Physical Design | Physical Design input files

In this article, we will discuss what are the inputs required to begin the physical design. In the previous article, we discussed the physical design flow and sanity checks before the floorplan. Inputs required for physical design can be categorised broadly into two types. Some inputs are mandatory in all the cases but some are … Read more

Sanity Checks before Floorplan in Physical Design

Sanity checks are an important step for physical design engineers to make sure that the inputs received for physical design are correct and consistent. Any issues in the input files may cause problems in the later stages. So it is important to perform the sanity checks in the initial stage that is when the design … Read more

Crosstalk Timing Window Analysis and Prevention Techniques

In the previous two articles, we have discussed signal integrity, crosstalk, crosstalk mechanisms, the parasitic capacitances associated to interconnects, crosstalk noise, crosstalk delay and its effects. In this article, we will discuss the timing window analysis of crosstalk and the prevention techniques of crosstalk. Timing Window Analysis Crosstalk timing window analysis is based on the … Read more

Crosstalk Noise and Crosstalk Delay – Effects of Crosstalk

In the previous article, we have discussed signal integrity, crosstalk, crosstalk mechanisms and the parasitic capacitances associated with interconnects. In this article, we will discuss the effects of crosstalk. Crosstalk has two major effects: Crosstalk glitch or crosstalk noise Crosstalk delta delay or crosstalk delay Crosstalk glitch In order to explain the crosstalk glitch, we … Read more

Signal Integrity and Crosstalk effect in VLSI

“According to a research conducted by Collett International Research Inc., one in five chips fails because of the signal integrity.” In this article, we will discuss a very important issue of VLSI design called signal integrity and crosstalk which are responsible for the failure of many ASICs now a day. We will discuss signal integrity … Read more

Latch-up Prevention in CMOS Logics

Before discussing the prevention techniques of Latch-up issue, let’s recall the key factor of the latch-up issue first. The following two factors are important for the latch-up issue. High resistance of n-well and p-substrate β1 x β2 >  1                                                    Figure-1: Latch-up formation Figure-1 … Read more

Standard Cells in ASIC Design | Standard Cells in VLSI

Standard cells are well defined and pre-characterized cells used in ASIC (Application Specific Integrated Circuit) Design flow as basic building blocks. All these cells are equal in height and can easily fit into the standard cell row. Standards cells are highly reusable and save lots of ASIC design time. Standard Cell Layout All the Standard … Read more

ASIC Design Flow – An Overview

In this post, ASIC (Application Specific Integrated Circuit) Design flow has been explained. The very first step of ASIC flow is design specification, which comes from the customer end. Where customer writes down the specification of the chip basically the functionality which he wants to develop in a chip.  The whole design process is going through various … Read more