Latch-up Prevention in CMOS Logics

Before discussing the prevention techniques of Latch-up issue, let’s recall the key factor of the latch-up issue first. The following two factors are important for the latch-up issue. High resistance of n-well and p-substrate β1 x β2 >  1                                                    Figure-1: Latch-up formation Figure-1 … Read more

Standard Cells in ASIC Design | Standard Cells in VLSI

Standard cells are well defined and pre-characterized cells used in ASIC (Application Specific Integrated Circuit) Design flow as basic building blocks. All these cells are equal in height and can easily fit into the standard cell row. Standards cells are highly reusable and save lots of ASIC design time. Standard Cell Layout All the Standard … Read more

ASIC Design Flow – An Overview

In this post, ASIC (Application Specific Integrated Circuit) Design flow has been explained. The very first step of ASIC flow is design specification, which comes from the customer end. Where customer writes down the specification of the chip basically the functionality which he wants to develop in a chip.  The whole design process is going through various … Read more