SDC is a short form of “Synopsys Design Constraint”. SDC is a common format for constraining the design which is supported by almost all Synthesis, PnR and other tools. Generally, timing, power and area constraints of design are provided through the SDC file and this file has extension .sdc. SDC file syntax is based on … Read more
Gate Oxide of a MOS transistor is the most sensitive part of a MOS device. Special care needs to be taken during fabrication of ASIC to protect it from any damages during fabrication steps and ASIC operation too. The antenna effect is a phenomenon that may cause damage to the gate oxide of MOS during … Read more
Before discussing the prevention techniques of Latch-up issue, let’s recall the key factor of the latch-up issue first. The following two factors are important for the latch-up issue. High resistance of n-well and p-substrate β1 x β2 > 1 Figure-1: Latch-up formation Figure-1 … Read more
Standard cells are well defined and pre-characterized cells used in ASIC (Application Specific Integrated Circuit) Design flow as basic building blocks. All these cells are equal in height and can easily fit into the standard cell row. Standards cells are highly reusable and save lots of ASIC design time. Standard Cell Layout All the Standard … Read more
What is a latch-up issue in CMOS design? In the simplest way, the latch-up issue can be defined as a formation of a direct path from VDD to GND terminal in the design, which will cause a huge current flow between the power and ground terminal. Latch-up Formation: Inside a CMOS (Complementary Metal Oxide Semiconductor) … Read more
In this post, we will discuss the LEF file used in the ASIC Design. LEF is a short form of Library Exchange Format. LEF file is written in ASCII format so this file is a human-readable file. A LEF file describing the Library has mainly two parts. Technology LEF Cell LEF Technology LEF Technology LEF … Read more
Lib file is a short form of Liberty Timing file. Liberty syntax is followed to write a .lib file. LIB file is an ASCII representation of timing and power parameter associated with cells inside the standard cell library of a particular technology node. Lib file is basically a timing model file which contains cell delay, … Read more
In this post, ASIC (Application Specific Integrated Circuit) Design flow has been explained. The very first step of ASIC flow is design specification, which comes from the customer end. Where customer writes down the specification of the chip basically the functionality which he wants to develop in a chip. The whole design process is going through various … Read more