Clock Tree Constraints in VLSI | ccopt file in Physical Design | CTS Constraints

Clock tree synthesis is a process of building and optimizing the clock tree in such a way that the clock gets distributed evenly and every sequential element gets the clock within a target global skew limit. To build the clock tree we have to provide certain constraints as input to the APR tool, which commonly … Read more

Inputs for Physical Design | Physical Design input files

In this article, we will discuss what are the inputs required to begin the physical design. In the previous article, we discussed the physical design flow and sanity checks before the floorplan. Inputs required for physical design can be categorised broadly into two types. Some inputs are mandatory in all the cases but some are … Read more