In this post, we will discuss the LEF file used in the ASIC Design. LEF is a short form of Library Exchange Format. LEF file is written in ASCII format so this file is a human-readable file. A LEF file describing the Library has mainly two parts.
- Technology LEF
- Cell LEF
Technology LEF part contains the information regarding all the metal interconnects, via information and related design rules whereas cell LEF part contains information related to the geometry of each cell. A sample snapshot is given below to show the information under technology LEF part.
Technology LEF part contains the following information
- LEF Version ( like 5.7 or 5.8 )
- Units (for database, time, resistance, capacitance)
- Manufacturing grids
- Design rules and other details of BEOL (Back End Of Layers)
- Layer name (like poly, contact, via1, metal1 etc)
- Layer type ( like routing, masterslice, cut etc)
- Prefered direction (like horizontal or vertical)
- Minimum width
- Sheet resistance
A snapshot of LEF file for the layer section and different dimension of metal interconnect has show bellow
Cell LEF part contains the information related to each cell present in the standard cell library in separate sections. For example here is a snapshot is presented to understand the format in a better way.
Cell LEF basically contains the following information
- Cell name (like AND2X2, CLKBUF1 etc)
- Class ( like CORE or PAD)
- Origin 0 0
- Size (width x height)
- Symmetry ( like XY, X, Y etc)
- Pin Information
- Pin name (like A, B, Y etc)
- Direction (like input, output, inout etc )
- Use (like Signal, clock, power etc)
- Shape (Abutment in case of power pin)
- Layer (like Metal1, Metal2 etc )
- The rectangular coordinate of pin (llx lly urx ury)
A snapshot of the cell section of the LEF file is presented below.
A LEF file is used by the router tool in PnR design to get the location of standard cells pins to route them properly. So it is basically the abstract form of layout of a standard cell.