When writing synthesizable Verilog / System Verilog code, it is important to follow certain guidelines to ensure the code can be correctly synthesized into hardware using a synthesis tool. Here are some basic guidelines for writing synthesizable Verilog / System Verilog code: Clearly define modules and interfaces: To ensure clarity and consistency in your code, … Read more
The famous quote by Richard Feynman that motivated towards the development of quantum computers is, “Nature isn’t classical, dammit, and if you want to make a simulation of nature, you’d better make it quantum mechanical, and by golly, it’s a wonderful problem, because it doesn’t look so easy.” It’s important to know that the principle … Read more
Code: SAM4Y022023PD Experience level: 4 Year Profile: Physical Design Engineer The following interview questions have been shared by a member of our team VLSI community who has recently appeared for a 3-year experienced open position in physical design and Synthesis domain. We thank you a lot for sharing these questions and encourage … Read more
In physical design domain, there are mainly two EDA tools which are widely used in ASIC Industry. One is Cadence Innovus and the other is ICC2 from Synopsys. Both the tools are equally good and continous advancement is going on. In this article you will get an overview of a very popular dbGet command of … Read more
In any modern electronic chip, there are multimillion logic gates inside it. To handle the design part of any such chips engineers need to take the help of CAD tools. The CAD tools used for ASIC development is called Electronic Design and Automation (EDA) tools. In the ecosystem of the semiconductor industry, EDA companies play … Read more
The electronics devices which we use on daily basis either come directly from a Semiconductor product company or the final chip developed by the product company is sold to some other company and they use the chip and make the final product and market it. Example: A Samsung mobile phone or a laptop of HP … Read more
If you are looking for a job change or you are a fresher and wanted to enter the VLSI Industry, then this article will help you a lot. It is difficult to find the company details or even a list of VLSI companies working in India. In this article, we have tried to prepare a … Read more
In this article, we are going to discuss the input files required in various stages of pnr and signoff. We can categorise the set of inputs into two parts, one is mandatory and the other is an optional set of inputs. A. Place and Route stages: I. Pre Placement Stage Gate level netlist Logical Library … Read more
Before starting this article, I would like to say this topic is highly sensitive and we are not supposed to reveal any foundry data. So Instead of making comments on any data which you know and I have not given here, you may mail me along with the reference link. The purpose of writing this … Read more
One scripting language without which it will be very difficult to survive in VLSI Industry, that would definitely be TCL (Tool Command Language). TCL is widely used everywhere in the VLSI industry because many tools are based on the tcl. We can directly interact with the tool using tcl CLI (Command Line Interpreter). It has … Read more
Code: CDN4Y072021PD Experience level: 4 Year Profile: Physical Design Engineer 1. Introduction and physical design experience 2. What major differences have you observed in the 7nm and 14nm process nodes? 3. What is the functionality of this circuit? (He drawn schematic in paint) 4. Do you think, is there any issue with the … Read more
The flip flop is the most commonly used sequential element in any ASIC design, especially the D-type flip-flop. In the D flip flop, the D indicates delay, which means the output is a delayed version of input D. Whereas a latch is the simplest and a basic sequential element. In general, there are two latches … Read more
The tie cell is a standard cell, designed specially to provide the high or low signal to the input (gate terminal) of any logic gate. The high/low signal can not be applied directly to the gate of any transistors because of some limitations of transistors, especially in the lower node. The limitation will also be … Read more
Low power ASIC design is the need of the hour, especially for hand-held electronics gadgets. In all hand-held products, the customer demands more battery life. This could be possible only if our SoC (System on Chip) inside the gadget consumes lesser power. There are various low-power design techniques that are being implemented the reduce the … Read more
Code: EXIM4Y062021PD Experience level : 3 years Brief Introduction and major projects? Tell me the most challenging part of your recent project How does the lockup latch help to fix hold violations? If we add a lockup latch, it might violate the setup? How will we fix it further? How did you … Read more
Code: CDN5Y062021PD Experience level: 5 Years For Application Engineer What are the major differences between 7nm and 12/14nm technology nodes? What are the new DRC rules in the 7nm technology node? What is the via-piller? What is double patterning? How many layers have double patterning in the 7nm node? How … Read more
Placement is a very important stage of physical design where all the standard cells get placed inside the core boundary. Overall QoR of the design greatly depends on the fact that how well placement is done. You must have noticed that the placement stage takes quite a large runtime. Actually, the tool performs various steps … Read more
Clock tree synthesis is a process of building and optimizing the clock tree in such a way that the clock gets distributed evenly and every sequential element gets the clock within a target global skew limit. To build the clock tree we have to provide certain constraints as input to the APR tool, which commonly … Read more
Most of the EDA tools used in the VLSI Industry are designed for use in UNIX operating system. These tools must require licenses to work which can be purchased from EDA Companies or a company that is authorized for sales and supports. Synopsys tools can be purchased either from www.synopsys.com or from authorized sales and support … Read more
If a simple question comes before you that “What will impact on the delay of a standard cell if temperature varies? ” Are you going to answer straightforward the delay of the cell will increase with temperature OR The delay of the cell will decrease with temperature? If you are going with either of the above … Read more