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In this article, we are going to discuss the input files required in various stages of pnr and signoff. We can categories the set of inputs into two parts, one is mandatory and the other is an optional set of inputs.


A. Place and Route stages:

 

I. Pre Placement Stage

    • Gate level netlist 
    • Logical Library
    • Physical Library
    • SDC file

        Optional inputs

    • Block partition def
    • Pin def
    • Power plan script
    • Welltap placement rule
    • Macro placement guidelines
    • MMMC Setup file
    • EndCap, Decap cell list
    • Spare Cell module definition and rule

Note:  (i) Logical Library, Physical Library and SDC file will be required in each stage.

            (ii) Netlist will get modified in each stage and an updated netlist will be used in the next stage. 


II. Placement

    • Preplace database

        Optional Inputs

    • Placement blockage script
    • Path groups script
    • Placement setting script 
    • Timing and Congestion Optimization scripts
    • Clock tree constraints (In case of Early Clock Flow)

III. CTS

    • Placement database
    • Clock tree constraints

IV. Route

    • CTS database

V. Chip Finish

    • Route database
    • Filler cell list

B. Metal Fill

    • OASIS/GDS of Chip finish stage

C. RC Extraction

    • ICT File / Quantus Techfile (qrcTechFile)
    • MMMC setup file
    • LEF
    • DEF
    • Merged OASIS/GDS file


D. IR Analysis


Technology/Library Data

    • LEF file (.lef)
    • LIB file (.lib)
    • Technology file (.tech)
    • GDS file of standard cells (.gds)
    • GDS Layer map file
    • Device model file*
    • SPICE Netlist of Standard cells* 

Design Data

    • DEF file
    • Netlist file
    • SPEF file
    • STA File*  (Timing Window, slew, instance frequency, clock domain info)
    • VCD file*
    • PLOC file*
* Files required only for dynamic analysis 

Types of Analysis:

I. Static IR Analysis

II. Dynamic IR Analysis

III. EM Analysis

 



E. Static Timing Analysis

  • Design Netlist 
  • SDC
  • LIB
  • SPEF
  • MMMC view definition file

Optional inputs:

  1. Instance-based IR drop file
  2. SI library
  3. Base/Incr Delay annotation file

F. Physical Verification

I. DRC

    • Merged GDS file
    • DRC RuleDeck file 

II. Antenna

    • Merged GDS file
    • Antenna RuleDeck file

III. Layout Vs Schematic Check (LVS)

    • PD Netlist
    • Merged GDS file 

IV. Logic Equivelence Check (LEC)

    • Golden Netlist
    • PD Netlist
    • LEC Constraints (if any) 

 In case you find anything missing or need a correction, please let me know in the comment section.


Thank You!

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