Physical Design Interview Question for experience level 3 Years, Question Set -10

Code: SAM4Y022023PD
Experience level: 4 Year
Profile: Physical Design Engineer


The following interview questions have been shared by a member of our team VLSI community who has recently appeared for a 3-year experienced open position in physical design and Synthesis domain. We thank you a lot for sharing these questions and encourage others to share your interview experience.  You can mail your interview questions at (We keep your identity confidential if you don’t want to share) For more such interview questions please visit our interview section.

After a formal introduction, the interviewer moved to the following discussion. Here is the list of questions that I can recall after the interview.

1. For which client are you working currently? 
2. What were your roles and responsibilities in the last project?

3. Have you performed sanity checks for your blocks?
4. If there are linking issues, what would be your approach to resolve those?
5. What are the things you are checking in check_timimg?
6. How will you resolve the things present in check_timing ( like timing loops, reasons for no_clock, unconstrained endpoints)
7. In ASIC design flow, where we perform sta and check timings (I said full ASIC flow, he asked where we will check timing in Asic flow after synthesis timing will check)
9. What is Synthesis and what are the outputs of synthesis?
10. What are the inputs for STA?

11. What is a DEF file and what it contains?
12. Have you ever run DMSA? What are the inputs required to run DMSA?
13. What are the differences between logical ecos and physical ecos?
14. Why do we need to check timing in scan mode?
15. Could you tell me the command (icc2 or innovus ) to get a list of all latches present in the design?
16. How can we get all the macros present in the block in the pt shell? let me know the exact command.
17. Define setup timing and fixes, other than optimization in data path what are the other ways to fix setup violations
18. Could you explain clock push and pull concepts?
19. If ICG pin is there can you find out a list of flops for that pin?
20. How will you proceed to fix the max transition violation?

21. Can you tell me the exact command to fix max fanout by load splitting method?
22. How will you report the transition value on a particular pin of a logic cell?
23. How can we report crosstalk on a pin?
24. Explain the setup timing equation?
25. What is a hold timing violation, explain the mathematical equation for hold timing. Way to fix the hold violation and where will check the margin for this hold fixes for clock pushing and pulling
26. What happens exactly in the DMSA timing fix?
27. Any difference between normal pt_shell and dmsa pt_shell?
28. What is the command to fix the setup in dmsa session?
29. If a pin is there how u will get how many clocks conncted to that pin
30. If a clock is there how u will know the period for that clock

31. If there are three clocks A,B, and C, A nd B are synchronous with each other and C is asynchronous with that A nd B what is the command to define these three clocks as asynchronous?
32. How will you get the relation for the defined clocks?
33. What are virtual clocks use of virtual clocks, and how u will define those?
34. How will u define the relation between in to reg, reg to out?
35. What are AOCV and POCV?
36. Where will we get AOCV values?
37. What is sigma, and which one is more accurate between 3sigma and 5sigma?
38. What is PBA and GBA?
39. Let me know the main switches of the report_timing command.
40. How do you analyze the timing report?

41. What are the reasons for setup violations?
42. Difference between HVT, LVT, and ULVT cell type?
43. How do u define a multicycle path?
44. What are the instance name and ref name, which are repeated in these two?
45. Command to get ref_name when we have cell name?
46. What is the difference between latch and flops?
47. What is the use of a def file in STA?

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