50 most useful dbGet commands for Innovus

In physical design domain, there are mainly two EDA tools which are widely used in ASIC Industry. One is Cadence Innovus and the other is ICC2 from Synopsys. Both the tools are equally good and continous advancement is going on. In this article you will get an overview of a very popular dbGet command of … Read more

VLSI EDA Companies in India | Top EDA Companies

In any modern electronic chip, there are multimillion logic gates inside it. To handle the design part of any such chips engineers need to take the help of CAD tools. The CAD tools used for ASIC development is called Electronic Design and Automation (EDA) tools.  In the ecosystem of the semiconductor industry, EDA companies play … Read more

VLSI Product Companies in India | Top 30 Semiconductor Product Companies

The electronics devices which we use on daily basis either come directly from a Semiconductor product company or the final chip developed by the product company is sold to some other company and they use the chip and make the final product and market it. Example: A Samsung mobile phone or a laptop of HP … Read more

Top 20 TCL syntax helpful to improve TCL scripting skill for VLSI Engineers

One scripting language without which it will be very difficult to survive in VLSI Industry, that would definitely  be TCL (Tool Command Language). TCL is widely used everywhere in the VLSI industry because many tools are based on the tcl. We can directly interact with the tool using tcl CLI (Command Line Interpreter).  It has … Read more

Interview questions for experienced Physical Design Engineer, Question set – 9

  Code: CDN4Y072021PD Experience level: 4 Year Profile: Physical Design Engineer 1. Introduction and physical design experience 2. What major differences have you observed in the 7nm and 14nm process nodes? 3. What is the functionality of this circuit? (He drawn schematic in paint) 4. Do you think, is there any issue with the above circuit? … Read more

Flip-flop and Latch : Internal structures and Functions

The flip flop is the most commonly used sequential element in any ASIC design, especially the D-type flip-flop. In the D flip flop, the D indicates delay, which means the output is a delayed version of input D.  Whereas a latch is the simplest and a basic sequential element. In general, there are two latches … Read more

Integrated Clock Gating (ICG) Cell in VLSI

 Low power ASIC design is the need of the hour, especially for hand-held electronics gadgets. In all hand-held products, the customer demands more battery life. This could be possible only if our SoC (System on Chip) inside the gadget consumes lesser power. There are various low-power design techniques that are being implemented the reduce the … Read more

Physical Design Interview Questions for 3 years experience , Question set – 8

Code: EXIM4Y062021PD Experience level : 3 years Brief Introduction and major projects? Tell me the most challenging part of your recent project How does the lockup latch help to fix hold violations? If we add a lockup latch, it might violate the setup? How will we fix it further? How did you fix SigEM? What … Read more

Physical Design Interview Questions : Question set -7

  Code: CDN5Y062021PD Experience level: 5 Years For Application Engineer What are the major differences between 7nm and 12/14nm technology nodes? What are the new DRC rules in the 7nm technology node? What is the via-piller? What is double patterning? How many layers have double patterning in the 7nm node? How tool performs placement steps? … Read more

Placement Steps in Physical Design

Placement is a very important stage of physical design where all the standard cells get placed inside the core boundary. Overall QoR of the design greatly depends on the fact that how well placement is done. You must have noticed that the placement stage takes quite a large runtime. Actually, the tool performs various steps … Read more

Clock Tree Constraints in VLSI | ccopt file in Physical Design | CTS Constraints

Clock tree synthesis is a process of building and optimizing the clock tree in such a way that the clock gets distributed evenly and every sequential element gets the clock within a target global skew limit. To build the clock tree we have to provide certain constraints as input to the APR tool, which commonly … Read more

Temperature Inversion in VLSI

If a simple question comes before you that “What will impact on the delay of a standard cell if temperature varies? ” Are you going to answer straightforward the delay of the cell will increase with temperature OR The delay of the cell will decrease with temperature? If you are going with either of the above … Read more

Interview questions asked for DFT Engineer (Fresher) – Question Set – 07

  Code: INTL0Y032021DFT This interview was held for the position of DFT Engineer with 0 years of experience. I personally felt the questions are good and generic which will help the freshers in other domains too. Round-1: 1) Differences between MOSFET and FINFET ?2) Puzzle:  A blind man walking in a desert has 2 red pills … Read more

Multi Bit Flip Flop Vs Single Bit Flip Flops

In modern ASIC design use of multi-bit flip flops (MBFF) has increased due to its various promising advantages of MBFF over single-bit flip flop (SBFF). Traditionally we study only a single-bit flip flop in our academics. So it becomes important to understand the design of multi-bit flip-flops, how it works, and what are the advantages/disadvantages … Read more

EDA tools in ASIC Industry

  We have noticed that when a person enters into the ASIC industry, He/She comes across various EDA tools of different EDA companies.  It’s natural for experienced professionals that the name of tools/company easily gets remembered, but for the freshers, they often forget the name because it’s new for them. It has also been noticed … Read more