Interview questions for experienced Physical Design Engineer, Question set – 9

Code: CDN4Y072021PD

Experience level: 4 Year
Profile: Physical Design Engineer
1. Introduction and physical design experience
2. What major differences have you observed in the 7nm and 14nm process nodes?
3. What is the functionality of this circuit? (He drawn schematic in paint)
4. Do you think, is there any issue with the above circuit? If so what would you suggest for improvement?
5. When clock gatting circuit has added in the design RTL/Synthesis/PnR?
6. What are the checks you perform before starting the floorplan?
7. What is a library check?
8. What are the information available inside the .lib file?
9. How is the timing of a cell defined in .lib file?
10. What if the .lib file is missing but .lef file is available for a cell? and similarly, if .lef file is missing but .lib file is present for a cell?

11. How do we define the core area for any block?
12. How do we decide the height and width of a block?
13. What are the guidelines we need to follow in macro placement?
14. Is there any rule for abutting the macros?
15. What steps exactly tool does in the placement stage?
16. Why do we use boundary cells?
17. Why can’t we use placement blockage at the end of each row in place on the boundary cell?
18. What was the target latency in your block and what has been achieved?
19. Can you explain the ccopt method?
20. Which flavour of Vt cell you used in the clock tree?

21. Which type of derating you have been used in your different projects?
22. Why do we start using POCV when we had AOCV derate?
23. What is the shielding of a net? How it works?
24. Have you used shielding in your block?
25. What is NDR?
26. What is the difference between shielding and NDR? Can we use only one of these two?
27. Where did you placed the clock gating cell, near the sink or source?
28. Can you tell me the advantage and disadvantages of placing ICG near the sink and near the source?
29. What is CPPR?
30. (A diagram has been drawn in paint as shown below) In this diagram can you tell me between which edges the setup and hold timing will be checked?
31. If we change the scenario like below, Now between which edge setup and hold will be checked? 
32. What is internal power and switching power?
33. What is the impact of the threshold voltage of a cell on the internal power and switching power?
34. What is the impact of IR drop in cell delay?
35. How do you fix the static IR drop?
36. What was the limit of dynamic IR drop in your recent project?

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