Clock Tree Constraints in VLSI | ccopt file in Physical Design | CTS Constraints

Clock tree synthesis is a process of building and optimizing the clock tree in such a way that the clock gets distributed evenly and every sequential element gets the clock within a target global skew limit. To build the clock tree we have to provide certain constraints as input to the APR tool, which commonly known as clock constraints, and in the case of the Innovus tool, this constraint file is popularly known as ccopt file.

In this article, we will learn some important clock tree constraints which are commonly used in every design and their actual meaning that why those constraints provided. Now a day it’s very common that if you are going to appear in an interview in physical design and your experience is in the bracket of 0-5Y, you have to face the question related to clock tree constraints in your interview.

clocks tree constraints:

  1. Clock tree cell list
  2. Preferred clock tree routing layers and Non-Default Rules (NDR)
  3. Target Skew
  4. Target Maximum Transition
  5. Target Maximum Capacitance
  6. Maximum Fanout
  7. Cell Density
  8. Cell Halo 

1. Clock tree cell list

We use clock inverters and clock buffers in the clock tree building. Sometimes we use only clock inverters and not clock buffers. We also use clock gating cells in the clock tree. so we have to provide the list of cells that we want to use in the clock tree.

set_ccopt_property inverter_cells {}
set_ccopt_property buffer_cells {}
set_ccopt_property clock_gating_cells {}
set_ccopt_property logic_cells {}

2. Preferred clock tree routing layers and Non-Default Rules (NDR)

We need to provide the top and bottom preferred routing layer for clock tree nets. We generally define here trunk and leaf net. the net which connects the clock to the sequential element’s clock pin is called the leaf net and the net which delivers the clock to the leaf net is called trunk net.

set_ccopt_property  -name trunckRoute -top_preferred_layer <> -bottom_preferred_layer <> -preferred_routing_layer_effort high -non_default_rule 2w2s

set_ccopt_property  -name leafRoute -top_preferred_layer <> -bottom_preferred_layer <> -preferred_routing_layer_effort high -non_default_rule 1w2s

3. Target skew

Skew balancing is one of the challenges in clock tree optimization. We provide a target skew as a clock tree constraint. PnR tool will try to balance the skew within the given limit of skew.

set_ccopt_property -target_skew <> 

4. Target Maximum Transition

We provide a max_trans limit for clock nets in the clock tree constraint. The tool will try to meet the max_trans limit.

set_ccopt_property -target_max_trans <> 

5. Target Maximum Capacitance

We provide a max_cap limit for clock nets in the clock tree constraint. The tool will try to distribute the load capacitance and try to meet the max_cap limit.

set_ccopt_property -target_max_capacitance <> 

6. Maximum fanout

We limit the maximum fanout of any instance in the clock tree through this constraint. Tool will try to build the clock tree by following this limit. 

set_ccopt_property -max_fanout <> 

7. Cell Density

A maximum cell density limit is mandatory for the clock tree instances.

set_ccopt_property -cell_density <>

8. Cell Halo

We need to provide a halo around the clock tree instance to avoid a denser placement which may cause IR / Crosstalk issue. So we provide halo constraints in the x and y direction over the cells.

set_ccopt_property -cell_halo_x <>  
set_ccopt_property -cell_halo_y <>  

These are the main constraint which we provide before the clock tree building. There are some more constraints but the main constraints are explained in the above sections. The following image summarizes the clock tree constraints.

CTS Constraints

Thank you! Any suggestions are welcomed in the comment section.

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