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Below image may help you to understand various parameters of FinFET. This image is taken from https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/
|Figure: FinFET structure and dimensions|
|1||Transistors||4th Gen FinFET||FinFET||Planner MOSFET|
|2||Gate Length (Lg)||16 nm||34 nm||24 nm|
|3||Fin Width (Wfin)||6 nm||NA|
|4||Fin Heigth (Hfin)||52 nm||37 nm||NA|
|5||Fin Pitch (Pfin)||30 nm||48 nm||NA|
|6||Contacted Poly Pitch (CPP)||57 nm (HD)
64 nm (HP)
|90 nm||117 nm|
|8||Minimum Metal Pitch (MMP)||40 nm||64 nm||90 nm|
|9||Standard Cell Height||240 nm (6T)|
|10||Transistor Density||91.2 M/mm2||28.9 M/mm2|
|11||6T SRAM bit cell size||0.027 um2||0.074 um2||0.127 um2 (HD)|
|12||Contact Trench Fill||Cobalt||Tungsten|
|13||Opertating Voltage||750 mV||800mv and 1V|
|14||Total Metal Layers||17||10|
|15||Double Patern Layers||7 (Fin, Poly, M0, M1, M2, M3, M4)|
Poly to M4 (SADP)
|17||DUV/EUV||193nm DUV + 13.5nm EUV||193nm DUV||193nm DUV|
|19||PG Routing||Dual M1 PG Structure|
|20||Mass Production Year||Q2 2018||2015||Q4 2011|
|21||Speed Improvement||30%, comapre 16nm with same power|
|40% , compare to 28nm with same power|
|22||Power Reduction||-55% compare to 16nm with same speed|
|-55% compare to 28nm with same speed|
|23||Density||3.3X compare to 16nm|
|24||Cut metal||Area reduction through
Cut metal layers.
Routers are cut metal aware