Experience level: 5 Years
For Application Engineer
- What are the major differences between 7nm and 12/14nm technology nodes?
- What are the new DRC rules in the 7nm technology node?
- What is the via-piller?
- What is double patterning?
- How many layers have double patterning in the 7nm node?
- How tool performs placement steps?
- Why do we perform scan chain reordering?
- What is scan mode, why do we need that?
- What is ECF (Early Clock Flow) flow?
- What are the benefits of ECF flow?
- Can you explain the CTS flow?
- What are the low power techniques used in data and clock paths?
- Where does the clock-gater use?
- Have you built a custom clock tree?
- What are the constraints you have given to the clock tree?
- How did you solve max_trans violations in the clock path?
- How to provide different clock tap points in H-Tree?
- How many clocks were there in your block?
- How were they related?
- How did you analyze the clock domain crossing paths?
- What is a lock-up latch and how does it helps in hold fixing?
- What was the target skew in your block?
- What value of skew you achieved?