Team VLSI We have noticed that when a person enters into the ASIC industry, He/She comes across various EDA tools of different EDA companies. It’s natural for experienced professionals that the name of tools/company easily gets remembered, but for the freshers, they often forget the name because it’s new for them. It has also been noticed … Read more
The tapeout is the final stage of the physical design process which definitely gives a big mental relax to the entire team involved in the project. The process of sending a clean layout file in form of gds/oasis to the foundry for fabrication after passing all the checks set by the foundry is termed as … Read more
A physical design engineer’s main focus is to achieve a decent Quality of Result (QoR) and optimized Power Performance and Area (PPA). The start of this journey begins with the Floorplan steps. What will you achieve at the end of PnR is depends on how good your floorplan is. In case of a macro dominating … Read more
In a broader sense, PnR (Place and Route) stage in physical design is basically Placement and Routing of all the instances present in the netlist in a defined core area in such a way that it should meet design rules and timing requirements. But before starting the actual automatic placement of instances by the PnR … Read more
Code: ALTRN0Y112020PD Some companies take a written test sometimes to shortlist the candidates before the interview process. This is a common process if the applicants are large in numbers. In such written test, the format is MCQ and some short questions. We are very thankful to one of our follower who has appeared in … Read more
Code: CYPR2Y102020PD Introduction and Experiences Self Introduction Explain about the projects that you have worked on. (Type of work and tools used) Synthesis Explain about Synthesis flow and what happens at each stage. (Inputs required, elaboration, generic stage, mapping and optimization stages) Explain about Synthesis Inputs. Differentiate between Logical and Physical Synthesis. (QoR impact between … Read more
Linux is an open-source operating system which is the first choice of every technocrat. For VLSI Design Engineers also most of the EDA tools are only compatible with Linux. In Linux, we interact with OS majorly with Command-Line Interface (CLI). In beginning, it might look a bit tedious as you have to remember lots … Read more
We all know that all the input and output pins of a block must be constrained in order to enable the PnR tool to optimize those interface paths. How to constrain an input or output pin will be discussed in this article. We will also discuss what are the actual meanings of these constraints and … Read more
Sometimes we need to place a particular group of standard cells or modules in a particular area (box). PnR tools allow us to do that. If I talk particularly about Cadence Innovus APR tool, It has three types of regions called Guide, Fence and Region through which we can provide guidance to the placement tool. … Read more
In the previous article, Best 5 books have recommended for Physical Design Engineer. While writing that article it was very difficult to make many books out of the list. So I thought it will be better to write another article on the best 25 books for VLSI Design. This list starts from the basic level … Read more
If you want to enhance your understanding and grow in any field, books can be your best buddy. Reading good books is a proven way to enhance understanding and develop depth knowledge of any domain. So I would like to say, the semiconductor industry is not an exception to this trend. If you want to … Read more
Code: QLCM2Y062020PV General Questions What are lambda based design rules? What is nm in 10nm technology node? Do you know about under bum density? Any prior experience of PnR? How do you import design in PnR? Why ID layers have been given in lower nodes (10nm)? Why nwell continuity is required? Have you done … Read more
Code: INTL2Y052020PV Floorplan What are the inputs for floorplan? In order to make sure integration is DRC clean, what rules or guidelines need to be followed at the floorplan stage? Can we abut macros on par boundary? How will judge the congestion between two IPs during floorplan stage without actual routing being done? Apart … Read more
Code: INTL2Y052020PV General What is done to solve congestion in lower and higher metal? How cell spreading helps in routing congestion? Cell spreading is done on what basis? What is DFM and why is it needed? What happens if DFM is not met? What are the inputs to GDSII file? What is crosstalk, Which checker … Read more
Code: MDTK3Y062019PDSYN Formal Introduction Whats are the projects you have done related to synthesis and Physical Design? Have you gone through Physical Design flow? What is synthesis? Whats are the inputs required for synthesis? What does constraint files contain? What is a multicycle path? What is a false path? Why do we perform STA? … Read more
Hello Guys, As you all know that the entry in the VLSI Industry is not easy for freshers, and it becomes more difficult especially if you don’t belong from tier-1 institutes of India. But keep good hopes always with you, people who are eligible, definitely get chance. So here important thing which I … Read more
Once a chip is fabricated and if any functionality issue is found in the chip or some functionality enhancement is required in the next fabrication. This might be a very challenging task without spare cells. But with the help of pre-placed spare cells, these changes can be done very easily. In this article, we will … Read more
Decap cells are basically a charge storing device made of the capacitors and used to support the instant current requirement in the power delivery network. There are various reasons for the instant large current requirement in the circuit and if there are no adequate measures have taken to handle this requirement, power droop or ground … Read more
There are high chances to get damaged the gate of standard cells placed at the boundary during the manufacturing of chip. To prevent such damages at the boundary we have a special kind of cell in the standard cell library is called end cap cell or boundary cell. Boundary cell not only protects the gate … Read more
Well tap cells (or Tap cells) are used to prevent the latch-up issue in the CMOS design. Well tap cells connect the nwell to VDD and p-substrate to VSS in order to prevent the latch-up issue. There is no logical function in well tap cell rather than proving a taping to nwell and p-substrate therefore … Read more