Team VLSI Standard cell library is an integral part of ASIC design flow and it helps to reduce the design time drastically. Standard cells used in the ASIC design is a part of a standard cell library along with some other file sets. In this article, we will discuss the important content inside the standard cell library … Read more
Electromigration is an important issue especially in lower technology node where the cross-sectional area of metal interconnects is very less. In this article, we will discuss the phenomenon of electromigration, the effects of electromigration and the ways to prevent the electromigration issue. Electromigration: When a high current density passes through a metal interconnect, the … Read more
In this article, we will discuss what are the inputs required to begin the physical design. In the previous article, we discussed the physical design flow and sanity checks before the floorplan. Inputs required for physical design can be categorised broadly into two types. Some inputs are mandatory in all the cases but some are … Read more
Sanity checks are an important step for physical design engineers to make sure that the inputs received for physical design are correct and consistent. Any issues in the input files may cause problems in the later stages. So it is important to perform the sanity checks in the initial stage that is when the design … Read more
In RTL to GDS flow, Physical Design is an important stage. In physical design, synthesized netlist, design constraints and standard cell library are taken as inputs and converted to a layout (gds file) which should be as per the design rules provided by the foundry. Further, this layout is sent to the foundry for the … Read more
In this article, we will discuss a widely used and very popular file used for data exchange from one EDA tool to another tool. Yes, we are going to discuss the Design Exchange Format or DEF file which is having extension .def. In this article, we will discuss the use of the def file, what … Read more
In this article, A comparative study of OCV (On Chip Variation), AOCV (Advance On Chip Variation) and POCV (Parametric On Chip Variation) have been done. Why and how a new variation model has evolved over the previous one and how it is better in terms of timing pessimism have also been discussed. Introduction: We have … Read more
In this article, we will discuss sources of On-Chip Variation (OCV) in VLSI, Why On Chip Variation occurs and how to take care of on chip variation in physical design. We will also discuss in very brief about the Advance On Chip Variation (AOCV) and Parametric On Chip Variation (POCV). Background: The final output which … Read more
In this article, we will discuss what is IR drop in ASIC design, Why IR drop issue occurs, what are the effects of IR drop and how to analyze and prevent the IR drop issue. What is IR drop issue: The power supply (VDD and VSS) in a chip is uniformly distributed through the metal rails … Read more
In the previous two articles, we have discussed signal integrity, crosstalk, crosstalk mechanisms, the parasitic capacitances associated to interconnects, crosstalk noise, crosstalk delay and its effects. In this article, we will discuss the timing window analysis of crosstalk and the prevention techniques of crosstalk. Timing Window Analysis Crosstalk timing window analysis is based on the … Read more
In the previous article, we have discussed signal integrity, crosstalk, crosstalk mechanisms and the parasitic capacitances associated with interconnects. In this article, we will discuss the effects of crosstalk. Crosstalk has two major effects: Crosstalk glitch or crosstalk noise Crosstalk delta delay or crosstalk delay Crosstalk glitch In order to explain the crosstalk glitch, we … Read more
“According to a research conducted by Collett International Research Inc., one in five chips fails because of the signal integrity.” In this article, we will discuss a very important issue of VLSI design called signal integrity and crosstalk which are responsible for the failure of many ASICs now a day. We will discuss signal integrity … Read more
In the last article, we discussed the antenna violation. How do antenna violations occur, and what is the mechanism to occur antenna effect or Plasma Induced Gate oxide damage. So in this article, we will discuss the solution part of the antenna effect, which is how to prevent the antenna violations. How to prevent antenna … Read more
SDC is a short form of “Synopsys Design Constraint”. SDC is a common format for constraining the design which is supported by almost all Synthesis, PnR and other tools. Generally, timing, power and area constraints of design are provided through the SDC file and this file has extension .sdc. SDC file syntax is based on … Read more
Gate Oxide of a MOS transistor is the most sensitive part of a MOS device. Special care needs to be taken during fabrication of ASIC to protect it from any damages during fabrication steps and ASIC operation too. The antenna effect is a phenomenon that may cause damage to the gate oxide of MOS during … Read more
Before discussing the prevention techniques of Latch-up issue, let’s recall the key factor of the latch-up issue first. The following two factors are important for the latch-up issue. High resistance of n-well and p-substrate β1 x β2 > 1 Figure-1: Latch-up formation Figure-1 … Read more
Standard cells are well defined and pre-characterized cells used in ASIC (Application Specific Integrated Circuit) Design flow as basic building blocks. All these cells are equal in height and can easily fit into the standard cell row. Standards cells are highly reusable and save lots of ASIC design time. Standard Cell Layout All the Standard … Read more
What is a latch-up issue in CMOS design? In the simplest way, the latch-up issue can be defined as a formation of a direct path from VDD to GND terminal in the design, which will cause a huge current flow between the power and ground terminal. Latch-up Formation: Inside a CMOS (Complementary Metal Oxide Semiconductor) … Read more
In this post, we will discuss the LEF file used in the ASIC Design. LEF is a short form of Library Exchange Format. LEF file is written in ASCII format so this file is a human-readable file. A LEF file describing the Library has mainly two parts. Technology LEF Cell LEF Technology LEF Technology LEF … Read more
Lib file is a short form of Liberty Timing file. Liberty syntax is followed to write a .lib file. LIB file is an ASCII representation of timing and power parameter associated with cells inside the standard cell library of a particular technology node. Lib file is basically a timing model file which contains cell delay, … Read more