In the previous article, we have discussed signal integrity, crosstalk, crosstalk mechanisms and the parasitic capacitances associated with interconnects. In this article, we will discuss the effects of crosstalk. Crosstalk has two major effects:
- Crosstalk glitch or crosstalk noise
- Crosstalk delta delay or crosstalk delay
In order to explain the crosstalk glitch, we will consider the following two cases. There might be many more similar cases.
Case-1: Aggressor net is switching low to high and victim net is at a constant low
|Figure-1: Crosstalk glitch (Raise)
In this case, the aggressor net switches from logic 0 to logic 1 and the victim net is at constant zero as shown in the figure-1. Now consider the node A, node V, Mutual capacitance Cm and the path from A to V. As node A start switching from low to high, a potential difference across the mutual capacitance gets developed and the mutual capacitor Cm starts charging. During this event, there is some leakage current which starts flowing from node A to node V through the mutual capacitance Cm due to the leaky nature of mutual capacitance. This leakage current will raise the potential of node V, which creates a raising spike or raising glitch on the victim net as shown in figure-1. The magnitude of this voltage or height of the glitch will depend on the various factors which will be discussed later.
So, whenever one net switches from low to high and other neighbouring net is supposed to remain constantly low, will get affected by the switching net and have a glitch on it. Now let’s discuss case-2 which is similar to case-1.
Case-2: Aggressor net is switching high to low and victim net is at a constant high
|Figure-2: Crosstalk glitch (Fall)
In this case, the aggressor net switches from logic 1 to logic 0 and the victim net is at constant high logic as shown in the figure-2. Now consider the node A, node V, Mutual capacitance Cm and the path from V to A. As node A start switching from high to low, a potential difference across the mutual capacitance gets developed and the mutual capacitor Cm starts charging through node V to node A. During this event, there is a leakage current which starts flowing from node V to node A through the mutual capacitance Cm due to the leaky nature of mutual capacitance. This leakage current will drop the potential of node V, which creates a falling spike or falling glitch on the victim net as shown in figure-2.
So, whenever one net switches from high to low and other neighbouring net is supposed to remain constantly high, will get affected by the switching net due to the mutual capacitance and have a falling glitch on it.
In case-1 and case-2 we have seen that if one net is switching and another neighbouring net is at constant logic and if they have mutual capacitance between them, the other net may get affected and that net may have a sudden raising or falling bump or spike. such a spike on the victim net is called a crosstalk glitch or crosstalk noise. Figure-3 shows the situations when there is a raise glitch or fall glitch.
|Figure-3: Raising and Falling glitch in crosstalk
Effects of crosstalk glitch
Does every glitch unsafe? The answer is it depends on the height of the glitch and the logical connection of the victim net. If the height of the glitch is within the noise margin low (NML), Such a glitch is considered a safe glitch. If the glitch height is above the noise margin high (NMH), such a glitch is considered a potentially unsafe glitch. In the case of a glitch, height is in between NMH and NML, this is an unpredictable case. Figure-4 shows the CMOS inverter transfer characteristics and Noise margins.
|Figure-4: CMOS transfer characteristics and Noise margin
As the technology node shrinks, the supply voltage also gets lowered. In lower supply voltage, noise margin will be lesser. If the noise margin is lesser it is more prone to have a potentially unsafe glitch. Figure-5 will help to understand this fact.
|Figure-5: Safe and unsafe glitch based on glitch heights
Figure-5 shows safe and unsafe glitches based on glitch heights. A safe glitch has no effect on the next logic of the victim net and the logic of the victim net will be treated as correct logic. But in other cases, the victim net’s logic may be treated as wrong logic due to the glitch and wrong data will be propagated which might cause the failure of the chip. Generally reset pins of memory is a constant logic and if such pin’s net has an unsafe crosstalk glitch, memory might get reset. Many other situations may occur which may cause chip failure due to the unsafe glitch.
But there are some cases where there are no effects of crosstalk glitches. For example, consider there is a two-input AND gate whose one input is tied at constant 0 and at the other input nets there is crosstalk happening. so whatever the effects of crosstalk, the output always will be Zero. similar cases are for many combinational logic where there would be no effects of crosstalk. Again in case of a glitch height is within the range of noise margin low.
Crosstalk glitch height
Crosstalk glitch will be safe or unsafe depending on the height of the crosstalk glitch and the logic pin from which the victim net is connected. So let’s investigate the factors on which the crosstalk glitch height depends. Crosstalk glitch height depends basically on three factors:
Aggressor’s drive strength
Victim’s drive strength
Closer the nets will have greater coupling capacitance. More the capacitance will have a larger glitch height. Drive strength of the aggressor and victim driver will also affect the glitch height. The high drive strength of the aggressor net will impact more the victim net. If the drive strength of the victim net is high, then it will not be easy to change its value, which means lesser will be the effect of crosstalk.
It was all about the crosstalk glitch or crosstalk noise, Now let’s move to the second effect which is crosstalk delta delay or crosstalk delay.
Crosstalk delay occurs when both aggressor and victim nets switch together. It has effects on the setup and hold timing of the design. Crosstalk delay may cause setup and hold timing violation. So it is important to do a crosstalk delay analysis and fix the timing considering the effect of crosstalk. Crosstalk could either increase or decrease the delay of a cell depending upon the switching direction of aggressor and victim nets. We will take two cases one when both nets switch in the same direction (high to low or low to high) and the other both the nets switch in opposite directions and will analyze the effect of crosstalk delay.Case-3: Aggressor and victim net switch in opposite directions
Let’s consider aggressor net switches from low to high logic and victim net switches from high to low (opposite). as shown in figure-6.
Case-4: Aggressor and victim nets switch in the same direction
Let’s consider the aggressor net switches from low to high logic and the victim net also switches from low to high (same direction). as shown in the figure-8.
As node A starts to transition from low to high at the same time, node V also starts switching from low to high. Suppose the aggressor net has high drive strength and so fast transition, a potential difference from node A to V will be developed after half of the transition happened. There is a coupling capacitance between A and V so the aggressor node will try to fast pull up the victim node. This will affect the smooth transition of the victim node from low to high and will have a bump after half of the transition and this will result in a decrease in the transition time of the victim net. Figure-9 shows the transition of nets. After crosstalk, the delay of the cell will be decreased by Δ and the new delay will be (D – Δ).
Effects of crosstalk delay
There are various effects of crosstalk delay on the timing of design. It could make unbalance a balanced clock tree, could violate the setup and hold timing. In this section, we will discuss some of them.
Effect on clock tree:
Crosstalk could unbalance a balanced clock tree. Crosstalk delay may increase or decrease the delay of clock buffers in the clock path and a balanced clock tree could be unbalanced as shown in the figure-10.
|Figure-10: Effect of crosstalk delay on clock tree
Let’s suppose the latency of path P1 is L1 and for the path P2 is L2. If the clock tree is balanced then L1 must be equal to L2. Now due let’s assume crosstalk delay occurs and it affects a clock buffer in clock path P2. Then now L1 will no more equal to L2 and now clock tree is not balanced. Here we have considered only one clock buffer got affected by the crosstalk delay but in reality, the effect could be in many places.
Effect on setup and hold timing:
Crosstalk delay can violate the setup timing. Figure-11, shows the data path, launch clock path and capture clock path.
|Figure-11: Effect of crosstalk delay on setup timing
For setup timing, data should reach the capture flop before the required time of capture flop. So if there is an increase of delay in the data path or launch clock path it may cause a setup violation. Setup violation may also happen if there is a decrease in delay on the capture clock path. These effects of crosstalk delay must be considered and fixed the timing.
Hold timing may be violated due to crosstalk delay. Figure-12, explains the situations where the hold time could violate due to crosstalk delay.
|Figure-12: Effect of crosstalk delay on hold timing
If there is a decrease in the delay of any cells in the data path and launch clock or there is an increase of delay of cells in the capture clock path due to crosstalk delay, It may result in the hold timing violation. Such cases must be considered and fix the timing.
This article is being too long, so we will stop here and will continue the remaining part, timing window analysis and crosstalk prevention techniques in the next article.