Introduction and Experiences
- Self Introduction
- Explain about the projects that you have worked on. (Type of work and tools used)
- Explain about Synthesis flow and what happens at each stage. (Inputs required, elaboration, generic stage, mapping and optimization stages)
- Explain about Synthesis Inputs.
- Differentiate between Logical and Physical Synthesis. (QoR impact between them)
- Wire load model(WLM), Mode, Types of trees
- Delay Calculation in WLM method. (Fanout based delay calculation)
Place and Route
- What are Inputs for PnR and Initial Checks need to be done?
- How to check for uniqueness of Netlist?
- Explain stages in PnR.
- Explain about useful skew and how it impacts the design.
- How do we achieve a better insertion delay?
- Explain about the CTS issues that you solved.
- Explain Physical Cells at the transistor level.
- Explain UPF, power domains, supply sets, isolation cells, retention registers.
- Feedthru insertion procedure and minimizing them. How you did Partitioning and improved partition related size, ports creation, Congestion.
- RTL Code for synchronous rst and asynchronous rst. (How do we write always block for this?)
- How do you write RTL code for FSM? (Explain about the number of always blocks required and significance of each one)
- Write RTL code for the traffic light system.
- Explain about the LEC procedure and issues faced and solved with respect to non-equivalent points.
- How do we fix Setup and Hold time violations?
- Explain about Dynamic and Leakage Power Consumption and methods to reduce them.
- If the chip is fabricated and hold violation exists. So what will you do? (other than saying that chip won’t work)
- Scripting related to finding empty modules, Unix commands.
These questions are shared by one of our active group members. Thanks a lot for your contribution!!!