Physical Verification Interview Questions : Question set – 2

Code: INTL2Y052020PV


  1. What is done to solve congestion in lower and higher metal?
  2. How cell spreading helps in routing congestion?
  3. Cell spreading is done on what basis?
  4. What is DFM and why is it needed?
  5. What happens if DFM is not met?
  6. What are the inputs to GDSII file?
  7. What is crosstalk, Which checker is used to detect the crosstalk?
  8. What is the difference between gate level netlist and layout netlist?
  9. How does a MOSFET work?
  10. What does the length of channel refer to?
  11. Explain transfer characteristics of a CMOS Inverter.


  1. Why Density needs to be maintained?
  2. What kind of densities are there?
  3. How do you know the density of each cell?
  4. If there are 100 plus density windows, then how to fix it?
  5. What happens if there are min or max density during fabrication?
  6. Whats are the projects you have done related to synthesis and Physical Design?


  1. What is DRC?
  2. Will the design be clean if halos are places properly in design?
  3. What are the types of DRC?


    1. What is LVS What it checks for?
    2. What are the inputs and outputs of LVS?
    3. What are hierarchical shorts?
    4. What are the inputs to generate the OASIS file?
    5. What is the full form of OASIS?
    6. What is the difference between ICC LVS and ICV LVS?
    7. In what format does the tool calculate the LVS?

      Post Credit: 

      These questions are shared by Karthik K Umesh, one of our group member. Thanks Karthik for sharing and helping people.

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