- What are the inputs for floorplan?
- In order to make sure integration is DRC clean, what rules or guidelines need to be followed at the floorplan stage?
- Can we abut macros on par boundary?
- How will judge the congestion between two IPs during floorplan stage without actual routing being done?
- Apart from IP alignment, what analysis have you done?
- What do you check at the placement stage?
Physical Only Cell
- What are the types of physical only cells in the design?
- In what stage are physical only cells placed in the design?
- Why are different types of physical only cells needed in design?
- Are you aware of latch-up in CMOS, can you elaborate?
- Explain how the parasitics are formed?
- What is the antenna effect?
- How can antenna effect be solved?
- Why metal jogging is done in the higher layer during antenna fixing?
- Which diode is used as an antenna diode?
- What parameters are considered while choosing the cutoff voltage of an antenna diode?
- How do you decide the number of diodes that needs to inserted for the failing net?
- On what basis have you inserted diodes?
- If M12 is the highest metal in the design and it has antenna, how do you fix it?
- Have you heard of nwell antenna?
- Can power net have an antenna effect?
- Can the antenna diode be placed in a different power from that of the affected cell?
- What is the impact of placing the antenna diode on timing?
- Where are the antenna diode terminals being connected?
- Voltage or current that is causing the antenna effect?
- How the gate area can be increased in antenna affected cell?
- How are you adding the antenna in antenna affected cell?
- What is the drive strength?
- What is the W/L ratio?
- Which layers are most susceptible to antenna violations, higher or lower layers?
- How do you handle antenna in clock net?
- What are types of ECOs?
- Where the ECOs generated and given to you or you prepared ECOs?