Kailash Prasad

Kailash Prasad is a Prime Minister Research Fellow at the Indian Institute of Technology Gandhinagar, specializing in hardware for machine learning, in-memory computing, CAD tool design, and SRAM memory subsystem design. He completed his B.Tech. in Electronics and Communication Engineering from the National Institute of Technology Arunachal Pradesh in 2018, and he is currently pursuing a Ph.D. in Electrical Engineering at IIT Gandhinagar. Kailash has received awards and recognition for his research, including the Intel India Research Fellowship in 2020. He is experienced in RTL to GDS flow for digital IC design and has led a team for tapeouts in UMC 65nm. His expertise also extends to SRAM memory subsystem design for digital and analog in-memory computing. Kailash is passionate about circuit design, teaching microelectronics and VLSI, and fostering the growth of VLSI engineers.

Writing Synthesizable Verilog/System Verilog code

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When writing synthesizable Verilog / System Verilog code, it is important to follow certain guidelines to ensure the code can be correctly synthesized into hardware using a synthesis tool. Here are some basic guidelines for writing synthesizable Verilog / System Verilog code: Clearly define modules and interfaces: To ensure clarity and consistency in your code, … Read more