Latch-up issue

Before discussing the prevention techniques of Latch-up issue, let’s recall the key factor of the latch-up issue first. The following two factors are important for the latch-up issue. High resistance of n-well and p-substrate β1 x β2 >  1                                                    Figure-1: Latch-up formation Figure-1 … Read more

What is a latch-up issue in CMOS design? In the simplest way, the latch-up issue can be defined as a formation of a direct path from VDD to GND terminal in the design, which will cause a huge current flow between the power and ground terminal. Latch-up Formation:  Inside a CMOS (Complementary Metal Oxide Semiconductor)  … Read more