Synthesis and Physical Design Interview Questions: Question Set -5

Code: CYPR2Y102020PD

Introduction and Experiences

1. Self Introduction
2. Explain about the projects that you have worked on. (Type of work and tools used)

Synthesis

1. Explain about Synthesis flow and what happens at each stage. (Inputs required, elaboration, generic stage, mapping and optimization stages)
2. Explain about Synthesis Inputs. 
3. Differentiate between Logical and Physical Synthesis. (QoR impact between them)
4. Wire load model(WLM), Mode, Types of trees
5. Delay Calculation in WLM method. (Fanout based delay calculation)

 

Place and Route

1. What are Inputs for PnR and Initial Checks need to be done?
2. How to check for uniqueness of Netlist?
3. Explain stages in PnR.
4. Explain about useful skew and how it impacts the design.
5. How do we achieve a better insertion delay?
6. Explain about the CTS issues that you solved.
7. Explain Physical Cells at the transistor level.
8. Explain UPF, power domains, supply sets, isolation cells, retention registers.
9. Feedthru insertion procedure and minimizing them. How you did Partitioning and improved partition related size, ports creation, Congestion.

RTL

1. RTL Code for synchronous rst and asynchronous rst. (How do we write always block for this?)
2. How do you write RTL code for FSM? (Explain about the number of always blocks required and significance of each one)
3. Write RTL code for the traffic light system.

SignOff

1. Explain about the LEC procedure and issues faced and solved with respect to non-equivalent points.
2. How do we fix Setup and Hold time violations?
3. Explain about Dynamic and Leakage Power Consumption and methods to reduce them.
4. If the chip is fabricated and hold violation exists. So what will you do? (other than saying that chip won’t work)
5. Scripting related to finding empty modules, Unix commands.