Contents

All Content of teamVLSI blog (clickable)

For a better experience for teamVLSI readers, Here is a topic-wise content list provided which will help to explore the blog in a better way. One can read any topics from this list by just clicking the name of the topics.

S.No.	Topics	No.	Topics
1	ASIC Flow	1	ASIC Design flow
		2	Physical Design flow in Details
		3	Inputs for Physical Design
		4	Sanity checks before floorplan in Physical Design
2	Files in VLSI	5	Inputs files required for PnR and Signoffs
		3*	Inputs for Physical Design
		6	LIB file in VLSI
		7	LEF file in VLSI
		8	DEF file in VLSI
		9	SDC file in VLSI
		10	Clock Tree Constraints File
3	Issues in VLSI	11	Latchup issue in VLSI
		13	Latchup prevention techniques in VLSI
		##	Well tap cells and latchup prevention mechanism
		14	Antenna effect in VLSI
		15	Antenna prevention techniques in VLSI
		16	Electromigration effect in VLSI
		17	Signal Intigrity and crosstalk effect in VLSI
		18	Crosstalk Noise and crosstalk delay effect
		19	Crosstalk timign window analysis and prevention techniques
		20	IR drop analysis in VLSI
		21	OCV in Physical Design
		22	OCV, AOCV and POCV in VLSI
4	Standard Cell	23	Standard cells library for ASIC Design
		24	Standard cells in ASIC Design
		25	Well Tap cells in Physical Design
		26	EndCap/Boundry cells in Physica Design
		27	Decap cells in Physical Design
		28	Spare Cells in Physical Design
		29	Integrated Clock Gating (ICG) Cell in VLSI
		30	Tie Cells in Physical Design
		31	Multi-bit flip flops Vs Single-bit flip flops
		32	Flip-flop and Latch : Internal structures and Functions

 

S.No.	Topics	No.	Topics
5	Short Topics	33	Temperature Inversion in VLSI
		31*	Multi-bit flip flops Vs Single bit flip flops
6	Pre Placement	34	Floorplan Strategy for macro dominating blocks
		35	Pre placement activities in VLSI Design
		36	Module Constraint types : Guide, Fence and Region
7	Placement	37	Placement Steps in VLSI
8	CTS	38	Clock Tree Constraints in VLSI
9	STA	##	Setup and Hold violation
		##	Setup fixing Techniques
		##	Hold Fixing Techniques
		39	IO Interfece analysis: IO constraints on block level
10	ECO	##	How to implement ECO in Physical Design
		40	ECO flow in Physical Design
11	Linux	41	Top 20 TCL syntax helpful to improve TCL scripting skills for VLSI Engineers
		##	Basics of sed commands
		##	Basics of awk command
		##	Basics of grep command
		42	50 Most usefull commands fro VLSI Engineers
12	EDA Tools	43	TSMC 7nm, 16nm and 28nm Technology node comparisons
		44	Installation of Synopsys tools
		##	Installation of MentorGraphics tools
		##	Installation of Cadence tools
		45	EDA tools in ASIC Industries
13	Interview Section	46*	Physical Design Interview Question for experience level 3 Years, Question Set -10
		46	Interview questions for experienced Physical Design Engineer, Question set – 9
		47	Physical Design Interview Questions for 3 years experience , Question set – 8
		48	Physical Design Interview Questions : Question set -7
		49	Written Test Question for Physical Design Engineer: Question Set – 6
		50	Synthesis and Physical Design Interview Questions: Question Set -5
		51	Physical Verification Interview Questions : Question set – 4
		52	Physical Verification Interview Questions : Question set – 3
		53	Physical Verification Interview Questions : Question set – 2
		54	Logic Synthesis and Physical Design Interview Questions : Question set – 1
		55	Basic Dos and Don’ts for Freshers in VLSI Interview
14	Books and Articles	56	Best 25 books on VLSI Design
		57	Top 5 books for Physical Design Engineer
15	VLSI Industry	58	Top EDA Companies in India
		59	Top VLSI Product Companies in India
		60	Top VLSI Service Companies in India

 

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