Physical Design Interview Questions for 3 years experience , Question set – 8

Code: EXIM4Y062021PD Experience level : 3 years Brief Introduction and major projects? Tell me the most challenging part of your recent project How does the lockup latch help to fix hold violations? If we add a lockup latch, it might violate the setup? How will we fix it further? How did you fix SigEM? What … Read more

Physical Design Interview Questions : Question set -7

  Code: CDN5Y062021PD Experience level: 5 Years For Application Engineer What are the major differences between 7nm and 12/14nm technology nodes? What are the new DRC rules in the 7nm technology node? What is the via-piller? What is double patterning? How many layers have double patterning in the 7nm node? How tool performs placement steps? … Read more

Interview questions asked for DFT Engineer (Fresher) – Question Set – 07

  Code: INTL0Y032021DFT This interview was held for the position of DFT Engineer with 0 years of experience. I personally felt the questions are good and generic which will help the freshers in other domains too. Round-1: 1) Differences between MOSFET and FINFET ?2) Puzzle:  A blind man walking in a desert has 2 red pills … Read more

Synthesis and Physical Design Interview Questions: Question Set -5

Code: CYPR2Y102020PD Introduction and Experiences Self Introduction Explain about the projects that you have worked on. (Type of work and tools used) Synthesis Explain about Synthesis flow and what happens at each stage. (Inputs required, elaboration, generic stage, mapping and optimization stages) Explain about Synthesis Inputs.  Differentiate between Logical and Physical Synthesis. (QoR impact between … Read more

Physical Verification Interview Questions : Question set – 4

  Code: QLCM2Y062020PV General Questions What are lambda based design rules? What is nm in 10nm technology node? Do you know about under bum density? Any prior experience of PnR? How do you import design in PnR? Why ID layers have been given in lower nodes (10nm)? Why nwell continuity is required? Have you done … Read more

Physical Verification Interview Questions : Question set – 3

  Code: INTL2Y052020PV Floorplan What are the inputs for floorplan? In order to make sure integration is DRC clean, what rules or guidelines need to be followed at the floorplan stage? Can we abut macros on par boundary? How will judge the congestion between two IPs during floorplan stage without actual routing being done? Apart … Read more

Basic Dos and Don’ts for Freshers in VLSI Interview

Hello Guys, As you all know that the entry in the VLSI Industry is not easy for freshers, and it becomes more difficult especially if you don’t belong from tier-1 institutes of India. But keep good hopes always with you, people who are eligible, definitely get chance. So here important thing which I want to … Read more