Input Files Required for PnR and Signoff Stages
In this article, we are going to discuss the input files required in various stages of pnr and signoff. We can categories the set of…
TSMC 7nm, 16nm and 28nm Technology node comparisons
Before starting this article, I would like to say this topic is highly sensitive and we are not supposed to reveal any foundry data. So…
Top 20 TCL syntax helpful to improve TCL scripting skill for VLSI Engineers
One scripting language without which it will be very difficult to survive in VLSI Industry, that would definitely be TCL (Tool Command Language). TCL is…
Interview questions for experienced Physical Design Engineer, Question set – 9
Code: CDN4Y072021PDExperience level: 4 YearProfile: Physical Design Engineer1. Introduction and physical design experience2. What major differences have you observed in the 7nm and 14nm process…
Flip-flop and Latch : Internal structures and Functions
The flip flop is the most commonly used sequential element in any ASIC design, especially the D-type flip-flop. In the D flip flop, the D…
Tie Cells in Physical Design
The tie cell is a standard cell, designed specially to provide the high or low signal to the input (gate terminal) of any logic gate.…
Integrated Clock Gating (ICG) Cell in VLSI
Low power ASIC design is the need of the hour, especially for hand-held electronics gadgets. In all hand-held products, the customer demands more battery life.…
Physical Design Interview Questions for 3 years experience , Question set – 8
Code: EXIM4Y062021PDExperience level : 3 yearsBrief Introduction and major projects?Tell me the most challenging part of your recent projectHow does the lockup latch help to…
Physical Design Interview Questions : Question set -7
Code: CDN5Y062021PDExperience level: 5 YearsFor Application Engineer What are the major differences between 7nm and 12/14nm technology nodes?What are the new DRC rules in the…
Placement Steps in Physical Design
Placement is a very important stage of physical design where all the standard cells get placed inside the core boundary. Overall QoR of the design…
Clock Tree Constraints in VLSI | ccopt file in Physical Design | CTS Constraints
Clock tree synthesis is a process of building and optimizing the clock tree in such a way that the clock gets distributed evenly and every…
Installation of Synopsys EDA tools
Most of the EDA tools used in the VLSI Industry are designed for use in UNIX operating system. These tools must require licenses to work…
Temperature Inversion in VLSI
If a simple question comes before you that "What will impact on the delay of a standard cell if temperature varies? " Are you going to…
Interview questions asked for DFT Engineer (Fresher) – Question Set – 07
Code: INTL0Y032021DFTThis interview was held for the position of DFT Engineer with 0 years of experience. I personally felt the questions are good and generic…
Multi Bit Flip Flop Vs Single Bit Flip Flops
In modern ASIC design use of multi-bit flip flops (MBFF) has increased due to its various promising advantages of MBFF over single-bit flip flop (SBFF).…
EDA tools in ASIC Industry
We have noticed that when a person enters into the ASIC industry, He/She comes across various EDA tools of different EDA companies. It's natural…
ECO Flow in Physical Design
The tapeout is the final stage of the physical design process which definitely gives a big mental relax to the entire team involved in the…
Floorplan Strategies for Macro Dominating Blocks
A physical design engineer's main focus is to achieve a decent Quality of Result (QoR) and optimized Power Performance and Area (PPA). The start of…
Pre-placement Activities in Physical Design
In a broader sense, PnR (Place and Route) stage in physical design is basically Placement and Routing of all the instances present in the netlist…